A method for synchronizing multiple threads includes a main thread instructing a processor to start and stop another thread. This type of synchronizing, however, does not include hardware support to allow one thread to transparently monitor the progress of another. Without suitable hardware support, it is difficult to perform inter-thread synchronization at a fine granularity.
Another way to synchronize multiple threads uses memory-based mechanism in which the threads are synchronized when they reach a barrier. Each thread has an address, and on reaching that address, the corresponding cache line is invalidated and the execution of the thread is halted and monitored by a filter. Only after all threads reach the barrier, the filter releases accesses to the lower level memory hierarchy and the execution of all threads resumes. This mechanism, however, also does not provide for point-to-point fine grained synchronization, and requires the participation of all processors involved in the synchronization.
Known mechanisms that watch for accesses to specific memory addresses target to support program debugging facilities, but not inter-thread communication. Those mechanisms do not allow for watching for accesses from specific processors only. They also require involvement from the processor that accesses the memory address being watched.
Current methods for synchronization between two threads that are based on hardware support are for atomic updates, such as the PowerPC load-linked (lwarx) and store-conditional (stwcx) instructions. However, all current methods require participation by both the application thread and the helper thread, and this requires that the code for the application thread be modified, and that it executes with some overhead in order to enable synchronization with the helper thread.